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www.fairchildsemi.com features 7-bit resolution 1/2 lsb linearity sample-and-hold circuit not required 20 msps conversion rate selectable output format available in 24-pin cerdip applications low-cost video digitzing medical imaging tv special effects video simulators radar data conversion description the TDC1047 is a 20 msps (megasample per second) full-parallel (?sh) analog-to-digital converter, capable of converting an analog signal with full-power frequency components up to 7 mhz into 7-bit digital words. use of a sample-and-hold circuit is not necessary. all digital inputs and outputs are ttl compatible. the TDC1047 consists of 127 clocked latching comparators, combining logic, and an output buffer register. a single convert signal controls the conversion operation. the unit can be connected to give either true or inverted outputs in binary or offset twos complement coding. the TDC1047 is pin and function compatible with the tdc1027, and offers increased performance with lower power dissipation. block diagram 1 2 7 126 127 63 64 nminv differential comparators (127) 127 to 7 encoder latch nlinv conv r r r r v in r t r 1 d 1-7 r 2 r b r 65-1047-01 rev. 1.0.0 TDC1047 monolithic video a/d converter 7-bit, 20 msps
TDC1047 product specification 2 functional description general information the TDC1047 has three functional sections: a comparator array, encoding logic, and output latches. the comparator array compares the input signal with 127 reference voltages to produce an n-of-127 code (sometimes referred to as a ?hermometer?code, as all the comparators referred to voltages more positive than the input signal will be off, and those referred to voltages more negative than the input signal will be on). the encoding logic converts the n-of-127 code into binary or offset twos complement coding, and can invert either output code. this coding function is controlled by dc signals on pins nminv and nlinv. the output latch holds the output constant between updates. power the TDC1047 operates from two supply voltages, +5.0v and -5.2v. the return for i cc , the current drawn from the +5.0v supply, is d gnd . the return for i ee , the current drawn from the -5.2v supply, is a gnd . all power and ground pins must be connected. reference the TDC1047 converts analog signals in the range v rb v in v rt into digital form. v rb (the voltage applied to the pin at the bottom of the reference resistor chain) and v rt (the voltage applied to the pin at the top of the reference resistor chain) should be between +0.1v and - 1.1v. v rt should be more positive than v rb within that range. the voltage applied across the reference resistor chain (v rt ? rb ) must be between 0.8v and 1.2v. the nominal voltages are v rt = 0.00v and v rb = -1.00v. these voltages may be varied dynamically up to 7mhz. due to variation in the reference currents with clock and input signals, r t and r b should be low-impedance-to-ground points. for circuits in which the reference is not varied, a bypass capacitor to ground is recommended. if the reference inputs are exercised dynamically as in an automatic gain control (agc) circuit, a low-impedance reference source is recommended. controls two function control pins, nminv and nlinv are provided. these controls are for dc (i.e., steady state) use. they permit the output coding to be either straight binary or offset twos complement, in either true or inverted sense, according to the output coding table. these pins are active low as signi?d by the pre? ??in the signal name. they may be tied to v cc for a logic 1 and d gnd for a logic 0. convert the TDC1047 requires a convert (conv) signal. a sample is taken (the comparators are latched) within the sampling time offset (t sto ) of a rising edge on the conv pin. the 127 to 7 encoding is performed on the falling edge of the conv signal. the coded result is transferred to the output latches on the next rising edge. the outputs hold the previous data a minimum time (t ho ) after the rising edge of the conv signal. this permits the previous conversion result to be acquired by external circuitry at that rising edge, i.e., data for sample n is acquired by the external circuitry while the TDC1047 is taking input sample n+2. analog input the TDC1047 uses strobed latching comparators which cause the input impedance to vary with the signal level, as comparator input transistors are cutoff or become active. for optimal performance, both v in pins must be used and the source impedance of the driving circuit must be less than 30 ohms. the input signal will not damage the TDC1047 if it remains within the range of v ee to + 0.5v. if the input signal is between the v rt and v rb references, the output will be a binary number between 0 and 127 inclusive. a signal outside this range will indicate either full-scale positive or full-scale negative, depending on whether the signal is off-scale in the positive or negative direction. outputs the outputs of the TDC1047 are ttl compatible, and capable of driving four low-power schottky ttl (54/74 ls) unit loads or the equivalent. the outputs hold the previous data a minimum time (t ho ) after the rising edge of the conv signal. pin assignments 1 2 3 4 5 6 7 8 9 10 11 12 v in r t a gnd d gnd nminv (msb) d 1 d 2 d 3 d 4 v cc v ee a gnd 24 23 22 21 20 19 18 17 16 15 14 13 v in r b a gnd d gnd conv d 7 (lsb) d 6 d 5 v cc nlinv v ee a gnd 24 lead ceramic dip 65-1047-02
product specification TDC1047 3 pin de?itions pin name pin number value pin function description power v cc 10, 16 +5.0v positive supply voltage v ee 11, 14 -5.2v negative supply voltage d gnd 4, 21 0.0v digital ground a gnd 3, 12, 13, 22 0.0v analog ground reference r t 2 0.00v reference resistor (top) r b 23 -1.00v reference resistor (bottom) controls nminv 5 ttl not most significant bit invert nlinv 15 ttl not least significant bit invert convert conv 20 ttl convert analog input v in 1, 24 0v to -1v analog signal input outputs d 1 6 ttl msb output d 2 ? 6 7, 8 , 9, 17, 18 ttl d 7 19 ttl lsb output
TDC1047 product specification 4 absolute maximum ratings 1 (beyond which the device will be damaged) notes: 1. absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating conditions. functional operation under any of these conditions is not implied. 2. applied voltage must be current limited to specified range. 3. forcing voltage must be limited to specified range. 4. current is specified as positive when flowing into the device. parameter min. max. unit supply voltages v cc (measured to d gnd ) -0.5 +7.0 v v ee (measured to a gnd ) -7.0 +0.5 v a gnd (measured to d gnd ) -0.5 +0.5 v input voltages conv, nminv, nlinv (measured to d gnd ) -0.5 +5.5 v v in , v rt , v rb (measured to a gnd ) +0.5 v ee v v rt (measured to v rb ) -2.2 +2.2 v output applied voltage (measured to d gnd ) 2 -0.5 5.5 v applied current, externally forced 3,4 -1.0 6.0 ma short circuit duration (single output in high state to ground) 1 sec temperature operating case -55 +125 c junction +175 c lead, soldering (10 seconds) +300 c storage -65 +150 c operating conditions parameters temperature range units standard extended min. nom. max. min. nom. max. v cc positive supply voltage (measured to d gnd ) 4.75 5.0 5.25 4.5 5.0 5.5 v v ee negative supply voltage (measured to a gnd ) -4.9 -5.2 -5.5 -4.9 -5.2 -5.5 v v agnd analog ground voltage (measured to d gnd ) -0.1 0.0 0.1 -0.1 0.0 0.1 v t pwl conv pulse width, (low) 14 14 ns t pwh conv pulse width, (high) 16 16 ns v il input voltage, logic low 0.8 0.8 v v ih input voltage, logic high 2.0 2.0 v l ol output current, logic low 4.0 2.0 ma i oh output current, logic high -0.4 -0.4 ma v rt most positive reference input 1 -0.1 0.0 0.1 -0.1 0.0 0.1 v v rb most negative reference inputs 1 -0.9 -1.0 -1.1 -0.9 -1.0 -1.1 v v rt- v rb voltage reference differential 0.8 1.0 1.2 0.8 1.0 1.2 v v in input voltage v rb v rt v rb v rt v
product specification TDC1047 5 note: 1. v rt must be more positive than v rb , and voltage reference differential must be within specified range. dc electrical characteristics note: 1. worst case, all digital inputs and outputs low. t a ambient temperature, still air 0 70 t c case temperature -55 125 c parameter test conditions temperature range units standard extended min. max. min. max. i cc positive supply current v cc = max, static 1 25 30 ma i ee negative supply current v ee = max, static 1 t a = 0 c to 70 c -170 ma t a = 70 c -135 ma t c = -55 c to 125 c -220 ma t c = 125 c -130 ma i ref reference current v rt , v rb = nom 35 50 ma r ref total reference resistance 28 20 w r in input equivalent resistance v rt , v rb = nom, v in = v rb 100 40 k w c in input capacitance 60 60 pf i cb input constant bias current v ee = max 150 300 m a i il input current, logic low v cc = max, v i = 0.5v conv -0.4 -0.6 ma nminv, nlinv -0.6 -0.8 ma i ih input current, logic high v cc = max, v l = 2.4v 50 50 m a i i input current, max input voltage v cc = max, v l = 5.5v 1.0 1.0 ma v ol output voltage, logic low v cc = min, l ol = max 0.5 0.5 v v oh output voltage, logic high v cc = min, i oh = max 2.4 2.4 v l os short circuit output current v cc = max, one pin to ground, one second duration. -30 -30 ma c l digital input capacitance t a = 25 c, f = 1mhz 15 15 pf operating conditions (continued) parameters temperature range units standard extended min. nom. max. min. nom. max.
TDC1047 product specification 6 ac electrical characteristics timing diagram figure 1. timing diagram system performance characteristics note: 1. in excess of quantization. parameter test conditions temperature range units standard extended min. max. min. max. f s maximum conversion rate v cc = min, v ee = min 20 20 msps t sto sampling time offset v cc = min, v ee = min 7 10 ns t d output delay v cc = min, v ee = min, load 1 30 35 ns t ho output hold time v cc = max, v ee = max, load 1 5 5 ns parameter test conditions temperature range units standard extended min. max. min. max. e li linearity error integral, independent v rt , v rb = nom 0.4 0.4 % e ld linearity error differential 0.4 0.4 % cs code size v rt , v rb = nom 30 170 30 170 % nominal v ot offset voltage top v in = v rt +50 +50 mv e ob offset voltage bottom v in = v rb -30 -30 mv t co temperature coefficient 20 20 m v/ c bw bandwidth, full power input 7 7 mhz t tr transient response, full-scale 10 10 ns snr signal-to-noise ratio 7mhz bandwidth, 20msps conversion peak signal/rms noise 1 mhz input 48 46 db 7 mhz input 46 44 db rms signal/rms noise 1 mhz input 39 37 db 7 mhz input 37 35 db e ap aperture error 50 50 ps dp differential phase error 1 f s = 4 x ntsc 1.5 1.5 degree dg differential gain error 1 f s = 4 x ntsc 2.5 2.5 % t pwh t pwl t sto t d t ho sample n conv analog input digital output sample n+1 data n-1 data n+1 data n sample n+2 1 f s 65-1047-03
product specification TDC1047 7 equivalent circuits figure 2. simplified analog input equivalent circuit figure 3. digital input equivalent circuit figure 4. output circuits output coding table note: 1. voltages are code midpoints when calibrated (see calibration section). step range binary twos complement true inverted true inverted -1.0000v fs 7.874mv step nminv=1 nlinv=1 0 0 0 1 1 0 000 0.0000v 0000000 1111111 1000000 0111111 001 ?.0078v 0000001 1111110 1000001 0111110 063 ?.4960v 0111111 1000000 1111111 0000000 064 ?.5039v 1000000 0111111 0000000 1111111 126 ?.9921v 1111110 0000001 0111110 1000001 127 ?.0000v 1111111 0000000 0111111 1000000 v in v ee v in c in c in is a nonlinear junction capacitance v rb is a voltage equal to the voltage on pin r b v eea i cb r in v rb 1-of-63 comparators v ee 65-1047-04 v cc 22k 15k input v cc +v cc output 40pf 1n3062 810 ? load 1 test load for delay measurements to output pin output equivalent circuit 65-1047-05
TDC1047 product specification 8 applications discussion calibration to calibrate the TDC1047, adjust v rt and v rb to set the 1st and 127th thresholds to the desired voltages in the block diagram. note that r 1 is greater than r, ensuring calibration with a positive voltage on r t . assuming a 0v to -1v desired range, continuously strobe the converter with -0.0039v on the analog input, and adjust v rt for output toggling between codes 00 and 01. then apply -0.9961v and adjust v rb for toggling between codes 126 and 127. instead of adjusting v rt , r t can be connected to analog ground and the 0v end of the range calibrated with a buffer offset control. r b is a convenient point for gain adjust that is not in the analog signal path. these techniques are employed in figure 5 typical interface circuit figure 5. typical interface circuit +5v video input r1 2 37.4 r2 3 39.2 ? r3 1k ? r4 2k ? r5 220 ? r7 1k ? r11 10k q1 2n2907 u3 a741c op-amp u2 ha-2539-5 op-amp c3 10 f 25v c7 0.1 f 50v r10 10k c12 1-6pf variable r6 2k ? r12 27 ? TDC1047 8, 10 1 3, 12, 13, 22 24 23 4, 21 20 11,14 5 19 18 17 8 7 6 r13 2.2k r14 2.2k r15 2.2k r17 2.2k r18 2.2k r19 2.2k 15 2 c9 0.1 f 50v c10 0.1 f 50v c1 10 f 25v l2 fair-rite 2743001111 l1 fair-rite 2743001111 10 3 3 4 2 + + 7 6 8 14 1 1 c8 0.1 50v c5 0.1 f 50v c2 70 f 25v c4 10 f 25v c11 0.1 f 50v d gnd v in v in v cc v ee a gnd r t r b d gnd d 1 (msb) d 7 (lsb) d 2 d 3 9 r16 2.2k d 4 d 5 d 6 nlinv nminv clk notes: 1. unless otherwise specified, all resistors are 1/4w, 2%. 2. r1 = z in ?0.001 1000 r2 1000 + r2 ( ( 3. r2 = 2v range v ref z in ( ( -5.2v conv c6 0.1 f 50v ?ain r9 multiturn pot 2k ? ?ffset r8 multiturn pot 2k ? + + + u4 lm313 reference 65-1047-06
product specification TDC1047 9 notes:
TDC1047 product specification 10 notes:
product specification TDC1047 11 mechanical dimensions 24 lead ceramic dip note 1 d s1 b2 e b1 e q a l ea c1 a a .225 5.72 symbol inches min. max. min. max. millimeters notes b1 .014 .023 .36 .58 .065 1.65 b2 .045 1.14 c1 .008 .015 .20 .38 e .500 .610 12.70 15.49 e .100 bsc 2.54 bsc l .120 .200 3.05 5.08 .015 .075 .38 1.91 .005 .13 3 6 8 4 8 2, 8 4 5, 9 ea .600 bsc 15.24 bsc 7 q s1 90 ? 105 ? 90 ? 105 ? a d 1.290 32.77 notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. index area: a notch or a pin one identification mark shall be located adjacent to pin one. the manufacturer's identification shall not be used as pin one identification mark. the minimum limit for dimension "b2" may be .023 (.58mm) for leads number 1, 12, 13 and 24 only. dimension "q" shall be measured from the seating plane to the base plane. this dimension allows for off-center lid, meniscus and glass overrun. the basic pin spacing is .100 (2.54mm) between centerlines. each pin centerline shall be located within .010 (.25mm) of its exact longitudinal position relative to pins 1 and 24. applies to all four corners (leads number 1, 12, 13, and 24). "ea" shall be measured at the center of the lead bends or at the centerline of the leads when " a " is 90 ? . all leads ?increase maximum limit by .003 (.08mm) measured at the center of the flat, when lead finish applied. twenty-two spaces.
product specification TDC1047 5/20/98 0.0m 001 stock# ds90001047 1998 fairchild semiconductor corporation life support policy fairchild? products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1 . life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2 . a critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com o r dering in f ormation p r oduct number t emperature range screening p a c k age p a c kage marking TDC1047b7c std t a = 0 c to 70 c commercial 24 lead ceramic dip 1047b7c TDC1047b7v ext? c = -55 c to 125 c mil-std-883 24 lead ceramic dip 1047b7v

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